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1 general description the ds3232m is a low-cost, extremely accurate, i 2 c real-time clock (rtc) with 236 bytes of battery-backed sram. the device incorporates a battery input and maintains accurate timekeeping when main power to the device is interrupted. the integration of the microelec - tromechanical systems (mems) resonator enhances the long-term accuracy of the device and reduces the piece- part count in a manufacturing line. the rtc maintains seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. the clock operates in either the 24-hour or 12-hour format with an am /pm indicator. two programmable time-of-day alarms and a 1hz output are provided. address and data are transferred serially through an i 2 c bidirectional bus. a precision temperature-compensated voltage reference and comparator circuit monitors the status of v cc to detect power failures, to provide a reset output, and to automatically switch to the backup supply when neces - sary. additionally, the rst pin is monitored as a pushbut - ton input for generating a microprocessor reset. see the block diagram for more details. applications power meters industrial applications features s timekeeping accuracy 5ppm (0.432 second/ day) from -40 n c to +85 n c s 236 bytes of battery-backed user sram s battery backup for continuous timekeeping s low power consumption s functionally compatible to ds3232 s complete clock calendar functionality including seconds, minutes, hours, day, date, month, and year with leap year compensation up to year 2100 s two time-of-day alarms s 1hz and 32.768khz outputs s reset output and pushbutton input with debounce s fast (400khz) i 2 c-compatible serial bus s +2.3v to +4.5v supply voltage s digital temp sensor with 3 n c accuracy s -40 n c to +85 n c temperature range s 8-pin so (150 mils) package s underwriters laboratories (ul) recognized typical operating circuit 19-6247; rev 1; 8/12 ordering information appears at end of data sheet. note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, go to: www.maxim-ic.com/errata . for related parts and recommended products to use with this part, refer to: www.maxim-ic.com/ds3232m.related ds3232m scl sda 32khz v bat v cc v cc cpu i/o port interrupts int/sqw rst push- button reset ds3232m 5ppm, i 2 c real-time clock with sram for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com.
ds3232m 5ppm, i 2 c real-time clock with sram 2 voltage range on any pin relative to gnd ........ -0.3v to +6.0v operating temperature range .......................... -40 n c to +85 n c storage temperature range ............................ -55 n c to +125 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions (t a = -40 n c to +85 n c, unless otherwise noted.) (note 1) electrical characteristicsfrequency and timekeeping (v cc or v bat = +3.3v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v cc = +3.3v, v bat = +3.0v, and t a = +25 n c, unless otherwise noted.) (note 1) dc electrical characteristicsgeneral (v cc = +2.3v to +4.5v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v cc = +3.3v, v bat = +3.0v, and t a = +25 n c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units 1hz frequency tolerance d f/f out measured over r 10s interval q 5 ppm 1hz frequency stability vs. v cc voltage d f/v q 1 ppm/v timekeeping accuracy tk a q 0.432 seconds/ day 32khz frequency tolerance d f/f out q 2.5 % parameter symbol conditions min typ max units supply voltage v cc 2.3 3.3 4.5 v v bat 2.3 3.0 4.5 logic 1 v ih 0.7 x v cc v cc + 0.3 v logic 0 v il -0.3 0.3 x v cc v parameter symbol conditions min typ max units active supply current (i 2 c active) i cca (note 2) 125 250 a standby supply current (i 2 c inactive) i ccs (notes 2, 3) 100 175 a
ds3232m 5ppm, i 2 c real-time clock with sram 3 dc electrical characteristicsgeneral ( continued ) (v cc = +2.3v to +4.5v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v cc = +3.3v, v bat = +3.0v, and t a = +25 n c, unless otherwise noted.) (note 1) dc electrical characteristicsv bat current consumption (v cc = 0v, v bat = +2.3v to +4.5v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v cc = 0v, v bat = +3.0v, and t a = +25 n c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units temperature conversion current (i 2 c inactive) i ccsconv 200 350 a power-fail voltage v pf 2.45 2.575 2.70 v logic 0 output (32khz, int /sqw, sda) v ol i ol = 3ma 0.4 v logic 0 output ( rst ) v ol i ol = 1ma 0.4 v logic 1 output (32khz) v oh active supply > 3.3v, i oh = -1ma 2.0 v active supply > 2.7v, i oh = -0.75ma 2.0 active supply > 2.3v, i oh = -0.14ma 2.0 output leakage (32khz, int /sqw, sda) i lo -0.1 +0.1 a input leakage (scl) i li -0.1 +0.1 a rst i/o leakage i ol -200 +10 a v bat leakage i batlkg t a = +25 n c -100 25 +100 na temperature accuracy temp acc v cc or v bat = +3.3v q 3 n c temperature conversion time t conv 10 ms pushbutton debounce pb db 250 ms reset active time t rst 250 ms oscillator stop flag (osf) delay t osf (note 4) 25 100 ms parameter symbol conditions min typ max units active battery current (i 2 c active) i bata (note 2) 25 75 a timekeeping battery current (i 2 c inactive) i batt en32khz = 0, intcn = 1 (note 2) 1.8 3.0 a temperature conversion current (i 2 c inactive) i battc 200 350 a data retention current (oscillator stopped and i 2 c inactive) i batdr t a = +25 n c 100 na
ds3232m 5ppm, i 2 c real-time clock with sram 4 note 1: limits are 100% tested at t a = +25c and t a = +85c. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. typical values are not guaranteed. note 2: includes the temperature conversion current (averaged). note 3: does not include rst leakage if v cc < v pf . note 4: the parameter t osf is the period of time the oscillator must be stopped for the osf flag to be set. note 5: the state of rst does not affect the i 2 c interface or rtc functions. note 6: interface timing shown is for fast-mode (400khz) operation. this device is also backward-compatible with standard mode i 2 c timing. note 7: c b = total capacitance of one bus line in picofarads. note 8: guaranteed by design and not 100% production tested. ac electrical characteristicspower switch (t a = -40 n c to +85 n c, unless otherwise noted.) (note 1, figure 2 ) ac electrical characteristicsi 2 c interface (v cc or v bat = +2.3v to +4.5v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v cc = +3.3v, v bat = +3.0v, and t a = +25 n c, unless otherwise noted.) (notes 1, 6, figure 1 ) parameter symbol conditions min typ max units v cc fall time, v pfmax to v pfmin t vccf 300 f s v cc rise time, v pfmin to v pfmax t vccr 0 f s recovery at power-up t rec (note 5) 250 300 ms parameter symbol conditions min typ max units scl clock frequency f scl 0 400 khz bus free time between stop and start conditions t buf 1.3 f s hold time (repeated) start condition t hd:sta 0.6 f s low period of scl t low 1.3 f s high period of scl t high 0.6 f s data hold time t hd:dat 0 0.9 f s data set-up time t su:dat 100 ns start set-up time t su:sta 0.6 f s sda and scl rise time t r (note 7) 20 + 0.1c b 300 ns sda and scl fall time t f (note 7) 20 + 0.1c b 300 ns stop set-up time t su:sto 0.6 f s sda, scl input capacitance c bin (note 8) 10 pf
ds3232m 5ppm, i 2 c real-time clock with sram 5 timing diagrams figure 1. i 2 c timing figure 2. power switch timing figure 3. pushbutton reset timing scl note: timing is referenced to v ilmax and v ihmin . sda stop start repeated start t buf t hd:sta t hd:dat t su:dat t su:sto t hd:sta t sp t su:sta t high t r t f t low t vccf t vccr t rec v pfmax v cc rst v pfmin t rst pb db rst
6 typical operating characteristics (t a = +25c, unless otherwise noted.) power-supply current vs. power-supply voltage ds3232m toc01 supply current (a) 60 80 100 120 140 160 180 200 40 supply voltage (v) 4.3 3.8 3.3 2.8 2.3 v bat = 2.3v, en32khz = 0, intcn = 1 t a = -40c t a = +85c t a = +25c v pf 1.0 1.5 2.0 2.5 battery current vs. battery voltage ds3232m toc02 battery current (a) 3.0 0.5 supply voltage (v) 4.3 3.8 3.3 2.8 2.3 v cc = 0v, en32khz = 0, intcn = 1 t a = -40c t a = +85c t a = +25c rst output voltage vs. output current ds3232m toc03 output current (ma) output voltage (v) 4 3 2 1 0.1 0.2 0.3 0.4 0.5 0.6 0 05 v cc = 2.45v int/ sqw output voltage vs. output current ds3232m toc04 output current (ma) output voltage (v) 8 6 4 2 0.1 0.2 0.3 0.4 0.5 0 01 0 v cc = 2.7v power-supply current vs. scl frequency ds3232m toc05 scl frequency (khz) supply current (a) 300 200 100 80 90 100 110 120 130 140 150 160 170 70 0 400 en32khz = 0, sda = inactive 2.6v 3.0v 4.0v thermometer error vs. temperature ds3232m toc06 temperature (c) thermometer error (c) 50 20 -10 -4 -3 -2 -1 0 1 2 3 4 5 -5 -40 80 v cc = 3.3v ds3232m 5ppm, i 2 c real-time clock with sram
ds3232m 5ppm, i 2 c real-time clock with sram 7 typical operating characteristics (continued) (t a = +25c, unless otherwise noted.) 1hz frequency error (measured every second) ds3232m toc07 time (seconds) frequency error (ppm) -8 -6 -4 -2 0 2 4 6 8 10 -10 03 0 25 20 15 10 5 v cc = 3.3v, t a = +25c 1hz frequency error (measured every second) ds3232m toc08 time (minutes) frequency error (ppm) -8 -6 -4 -2 0 2 4 6 8 10 -10 03 0 25 20 15 10 5 v cc = 3.3v, t a = +25c 1hz frequency error (delta from t0) ds3232m toc09 time (minutes) frequency error (ppm) 03 0 25 20 15 10 5 v cc = 3.3v, t a = +25c -4 -3 -2 -1 0 1 2 3 4 5 -5 1hz frequency error (10s thermal updates measured every second) ds3232m toc10 time (seconds) frequency error (ppm) -8 -6 -4 -2 0 2 4 6 8 10 -10 03 0 25 20 15 10 5 v bat = 3.3v, v cc = 0v, t a = +25c 1hz frequency error (1s thermal updates measured every second) ds3232m toc11 time (seconds) frequency error (ppm) -8 -6 -4 -2 0 2 4 6 8 10 -10 03 0 25 20 15 10 5 v bat = 3.3v, v cc = 0v, t a = +25c timekeeping accuracy vs. temperature ds3232m toc12 temperature (c) frequency eror (ppm) 80 60 40 20 0 -20 -150 -100 -50 0 50 -200 -40 typical 20ppm crystal, uncompensated ds3232m accuracy
ds3232m 5ppm, i 2 c real-time clock with sram 8 pin configuration pin description pin name function 1 32khz 32.768khz output (push-pull output, 50% duty cycle). if enabled (en32khz = 1), the 32khz output is active on v cc . if enabled for battery operation (bb32khz = 1), the output is also active on v bat . when disabled, the output is forced low. this pin can be left unconnected if not used. 2 v cc dc power pin for primary power supply. this pin should be decoupled using a 0.1 f f to 1.0 f f capacitor. connect to ground if not used. 3 int / sqw active-low interrupt or 1hz square-wave output. this open-drain pin requires an external pullup resistor connected to a supply at 4.5v or less. it can be left open if not used. this multifunction pin is determined by the state of the intcn bit in the control register (0eh). when intcn is set to logic 0, this pin outputs a 1hz square wave. when intcn is set to logic 1, a match between the timekeeping registers and either of the alarm registers activates the int /sqw pin (if the alarm is enabled). because the intcn bit is set to logic 1 when power is first applied, the pin defaults to an interrupt output with alarms disabled. 4 rst active-low reset. this pin is an open-drain input/output. it indicates the status of v cc relative to the v pf specification. as v cc falls below v pf , the rst pin is driven low. when v cc exceeds v pf , for t rst , the rst pin is pulled high by the internal pullup resistor. the active-low, open-drain output is combined with a debounced pushbutton input function. this pin can be activated by a pushbutton reset request. it has an internal 50k i (r pu ) nominal value pullup resistor to v cc . no external pullup resistors should be con - nected. if the oscillator is disabled, t rec is bypassed and rst immediately goes high. 5 gnd ground 6 v bat backup power-supply input. when using the device with the v bat input as the primary power source, this pin should be decoupled using a 0.1 f f to 1.0 f f low-leakage capacitor. when using the device with the v bat input as the backup power source, the capacitor is not required. if v bat is not used, connect to ground. the device is ul recognized to ensure against reverse charging when used with a primary lithium battery. go to www.maxim-ic.com/qa/info/ul for more information. 7 sda serial-data input/output. this pin is the data input/output for the i 2 c serial interface. this open-drain pin requires an external pullup resistor. the pullup voltage can be up to 4.5v, regardless of the voltage on v cc . 8 scl serial-clock input. this pin is the clock input for the i 2 c serial interface and is used to synchronize data movement on the serial interface. the pullup voltage can be up to 4.5v, regardless of the voltage on v cc . ds3232m v bat gnd rst 1 2 8 7 scl sda v cc int/sqw 32khz so top view 3 4 6 5 +
ds3232m 5ppm, i 2 c real-time clock with sram 9 detailed description the ds3232m is a serial real-time clock (rtc) driven by an internal, temperature-compensated, microelectrome - chanical systems (mems) resonator. the oscillator pro - vides a stable and accurate reference clock and main - tains the rtc to within q 0.432 seconds-per-day accu - racy from -40 n c to +85 n c. the rtc is a low-power clock/ calendar with two programmable time-of-day alarms. int / sqw provides either an interrupt signal due to alarm conditions or a 1hz square wave. the clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is auto - matically adjusted for months with fewer than 31 days, including corrections for leap year. the clock operates in either the 24-hour or 12-hour format with an am /pm indi - cator. the internal registers are accessible though an i 2 c bus interface. a temperature-compensated voltage refer - ence and comparator circuit monitors the level of v cc to detect power failures and to automatically switch to the backup supply when necessary. the rst pin provides an external pushbutton function and acts as an indica - tor of a power-fail event. also available are 236 bytes of general-purpose battery-backed sram. operation the block diagram shows the devices main elements. each of the major blocks is described separately in the following sections. block diagram ds3232m n n time-base resonator temp sensor interrupt or 1hz select divider int/sqw 1hz digital adjustment factory trim n 32khz gnd sda scl v bat v cc rst clock/calendar with alarm control and status registers sram i 2 c interface power control* p *selected power
ds3232m 5ppm, i 2 c real-time clock with sram 10 high-accuracy time base the temperature sensor, oscillator, and digital adjust - ment controller logic form the highly accurate time base. the controller reads the output of the on-board tempera - ture sensor and adjusts the final 1hz output to maintain the required accuracy. the device is trimmed at the factory to maintain a tight accuracy over the operating temperature range. when the device is powered by v cc , the adjustment occurs once a second. when the device is powered by v bat , the adjustment occurs once every 10s to conserve power. adjusting the 1hz time base less often does not affect the devices long-term timekeeping accuracy. the device also contains an aging offset reg - ister that allows a constant offset (positive or negative) to be added to the factory-trimmed adjustment value. power-supply configurations the ds3232m can be configured to operate on a single power supply (using either v cc or v bat ) or in a dual- supply configuration, which provides a backup supply source to keep the timekeeping circuits alive during absence of primary system power. figure 4 illustrates a single-supply configuration using v cc only, with the v bat input grounded. when v cc < v pf , the rst output is asserted (active low). temperature con - versions are executed once per second. figure 5 illustrates a single-supply configuration using v bat only, with the v cc input grounded. the rst output is disabled and is held at ground through the connection of the internal pullup resistor. temperature conversions are executed once every 10s. figure 6 illustrates a dual-supply configuration, using the v cc supply for normal system operation and the v bat supply for backup power. in this configuration, the power-selection function is provided by a temperature- compensated voltage reference and a comparator circuit that monitors the v cc level. when v cc is greater than v pf , the device is powered by v cc . when v cc is less than v pf but greater than v bat , the device is powered by v cc . if v cc is less than v pf and is less than v bat , the device is powered by v bat (see table 1 ). when v cc < v pf , the rst output is asserted (active low). when v cc is the presently selected power source, temperature conversions are executed once per second. when v bat is the presently selected power source, tem - perature conversions are executed once every 10s. figure 4. single supply (v cc only) figure 5. single supply (v bat only) figure 6. dual power supply v bat v cc +3.3v v bat v cc v bat v cc +3.3v
ds3232m 5ppm, i 2 c real-time clock with sram 11 table 1. power control to preserve the battery, the first time v bat is applied to the device the oscillator does not start up until v cc exceeds v pf or until a valid i 2 c address is written to the device. typical oscillator startup time is less than 1s. approximately 2s after v cc is applied, or a valid i 2 c address is written, the device makes a temperature measurement and applies the calculated correction to the oscillator. once the oscillator is running, it continues to run as long as a valid power source is available (v cc or v bat ), and the device continues to measure the tem - perature and correct the oscillator frequency. on the first application of v cc power, or (if v bat powered) when a valid i 2 c address is written to the device, the time and date registers are reset to 01/01/00 01 00:00:00 (dd/mm/ yy dow hh:mm:ss). v bat operation there are several modes of operation that affect the amount of v bat current that is drawn. while the device is powered by v bat and the serial interface is active, the active battery current i bata is drawn. when the serial interface is inactive, the timekeeping current i batt (which includes the averaged temperature-conversion current i battc ) is used. the temperature-conversion current i battc is specified since the system must be able to support the periodic higher current pulse and still maintain a valid voltage level. the data-retention current i batdr is the current drawn by the device when the oscillator is stopped ( eosc = 1). this mode can be used to minimize battery requirements for periods when maintaining time and date information is not necessary, e.g., while the end system is waiting to be shipped to a customer. pushbutton reset function the device provides for a pushbutton switch to be con - nected to the rst input/output pin. when the device is not in a reset cycle, it continuously monitors rst for a low-going edge. if an edge transition is detected, the device debounces the switch by pulling rst low. after the internal timer has expired (pb db ), the device con - tinues to monitor the rst line. if the line is still low, the device continuously monitors the line looking for a rising edge. upon detecting release, the device forces rst low and holds it low for t rst . rst is also used to indi - cate a power-fail condition. when v cc is lower than v pf , an internal power-fail signal is generated, which forces rst low. when v cc returns to a level above v pf , rst is held low for approximately 250ms (t rec ) to allow the power supply to stabilize. if the oscillator is not running when v cc is applied, t rec is bypassed and rst imme - diately goes high. assertion of the rst output, whether by pushbutton or power-fail detection, does not affect the devices internal operation. rst output operation and pushbutton monitoring are only available if v cc power is available. configuration condition i/o active i/o inactive rst v cc only (figure 4) v cc > v pf i cca i ccs inactive (high) v cc < v pf active (low) v bat only (figure 5) eosc = 0 i bata i batt disabled (low) eosc = 1 i batdr dual supply (figure 6) v cc > v pf i cca i ccs inactive (high) v cc < v pf v cc > v bat i cca v cc > v bat i ccs active (low) v cc < v bat i bata v cc < v bat i batt
ds3232m 5ppm, i 2 c real-time clock with sram 12 real-time clock (rtc) with the 1hz source from the temperature-compensated oscillator, the rtc provides seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. the clock operates in either the 24-hour or the 12-hour format with an am/ pm indicator. the clock pro - vides two programmable time-of-day alarms. int /sqw can be enabled to generate either an interrupt due to an alarm condition or a 1hz square wave. this selection is controlled by the intcn bit in the control register. i 2 c interface the i 2 c interface is accessible whenever either v cc or v bat is at a valid level. if a microcontroller connected to the device resets because of a loss of v cc or other event, it is possible that the microcontroller and devices i 2 c communications could become unsynchronized, e.g., the microcontroller resets while reading data from the device. when the microcontroller resets, the devices i 2 c interface can be placed into a known state by tog - gling scl until sda is observed to be at a high level. at that point the microcontroller should pull sda low while scl is high, generating a start condition. sram the ds3232m provides 236 bytes of general-purpose battery-backed read/write memory. the i 2 c address ranges from 14hCffh. the sram can be written or read whenever v cc or v bat is greater than the minimum oper - ating voltage. address map table 2 shows the address map for the devices time - keeping registers. during a multibyte access, when the address pointer reaches the end of the register space (12h), it wraps around to location 00h. on an i 2 c start or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. the time information is read from these sec - ondary registers, while the clock can continue to run. this eliminates the need to reread the registers in case the main registers update during a read. clock and calendar the time and calendar information is obtained by reading the appropriate register bytes. table 2 shows the rtc registers. the time and calendar data are set or initialized by writing the appropriate register bytes. the contents of the time and calendar registers are in the binary-coded decimal (bcd) format. the device can be run in either 12-hour or 24-hour mode. bit 6 of the hours register is defined as the 12-hour or 24-hour mode select bit. when high, the 12-hour mode is selected. in the 12-hour mode, bit 5 is the am /pm bit with logic-high being pm. in the 24-hour mode, bit 5 is the 20-hour bit (20C23 hours). the century bit (bit 7 of the month register) is toggled when the years register overflows from 99 to 00. the day-of-week register increments at midnight. values that correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals sunday, then 2 equals monday, and so on). illogical time and date entries result in undefined operation. when reading or writing the time and date registers, secondary buffers are used to prevent errors when the internal registers update. when reading the time and date registers, the secondary buffers are synchronized to the internal registers on any i 2 c start and when the register pointer rolls over to zero. the time information is read from these secondary registers, while the clock continues to run. this eliminates the need to reread the registers in case the main registers update during a read. the countdown chain is reset whenever the seconds register is written. write transfers occur on the acknowledge from the device. once the countdown chain is reset, to avoid rollover issues the remaining time and date registers must be written within 1s.
ds3232m 5ppm, i 2 c real-time clock with sram 13 table 2. timekeeping registers note: unless otherwise specified, the registers state is not defined when power is first applied. address bit 7 msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lsb function range 00h 0 10 seconds seconds seconds 00C59 01h 0 10 minutes minutes minutes 00C59 02h 0 12/ 24 am /pm 10 hours hour hours 1C12 + am /pm 00C23 20 hours 03h 0 0 0 0 0 day day 1C7 04h 0 0 10 date date date 01C31 05h century 0 0 10 month month month/century 01C12 + century 06h 10 year year year 00C99 07h a1m1 10 seconds seconds alarm 1 seconds 00C59 08h a1m2 10 minutes minutes alarm 1 minutes 00C59 09h a1m3 12/ 24 am /pm 10 hours hour alarm 1 hours 1C12 + am /pm 00C23 20 hours 0ah a1m4 dy/ dt 10 date day alarm 1 day 1C7 date alarm 1 date 1C31 0bh a2m2 10 minutes minutes alarm 2 minutes 00C59 0ch a2m3 12/ 24 am /pm 10 hours hour alarm 2 hours 1C12 + am /pm 00C23 20 hours 0dh a2m4 dy/ dt 10 date day alarm 2 day 1C7 date alarm 2 date 1C31 0eh eosc bbsqw conv na na intcn a2ie a1ie control 0fh osf bb32khz 0 0 en32khz bsy a2f a1f status 10h sign data data data data data data data aging offset 11h sign data data data data data data data temperature msb 12h data data 0 0 0 0 0 0 temperature lsb 13h swrst 0 0 0 0 0 0 0 test 14hCffh x x x x x x x x sram 00hCffh
ds3232m 5ppm, i 2 c real-time clock with sram 14 alarms the device contains two time-of-day/date alarms. alarm 1 can be set by writing to registers 07hC0ah. alarm 2 can be set by writing to registers 0bhC0dh. see table 2 . the alarms can be programmed (by the alarm enable and intcn bits in the control register) to activate the int /sqw output on an alarm match condition. bit 7 of each of the time-of-day/date alarm registers are mask bits ( table 2 ). when all the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers match the corresponding values stored in the time-of-day/date alarm registers. the alarms can also be programmed to repeat every second, minute, hour, day, or date. table 3 shows the possible settings. configurations not listed in the table result in illogical operation. the dy/ dt bits (bit 6 of the alarm day/date registers) con - trol whether the alarm value stored in bits 0C5 of that register reflects the day of the week or the date of the month. if dy/ dt is written to logic 0, the alarm is the result of a match with date of the month. if dy/ dt is written to logic 1, the alarm is the result of a match with day of the week. when the rtc register values match alarm register settings, the corresponding alarm flag a1f or a2f bit is set to logic 1. if the correspond - ing alarm interrupt enable a1ie or a2ie bit is also set to logic 1, the alarm condition activates the int /sqw signal if the intcn bit is set to logic 1. the match is tested on the once-per-second update of the time and date registers. table 3. alarm mask bits dy/ dt alarm 1 register mask bits (bit 7) alarm rate a1m4 a1m3 a1m2 a1m1 x 1 1 1 1 alarm once a second x 1 1 1 0 alarm when seconds match x 1 1 0 0 alarm when minutes and seconds match x 1 0 0 0 alarm when hours, minutes, and seconds match 0 0 0 0 0 alarm when date, hours, minutes, and seconds match 1 0 0 0 0 alarm when day, hours, minutes, and seconds match dy/ dt alarm 2 register mask bits (bit 7) alarm rate a2m4 a2m3 a2m2 x 1 1 1 alarm once per minute (00 seconds of every minute) x 1 1 0 alarm when minutes match x 1 0 0 alarm when hours and minutes match 0 0 0 0 alarm when date, hours, and minutes match 1 0 0 0 alarm when day, hours, and minutes match
ds3232m 5ppm, i 2 c real-time clock with sram 15 control register (0eh) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 eosc bbsqw conv na na intcn a2ie a1ie 0 0 0 1 1 1 0 0 bit 7 eosc : enable oscillator. when set to logic 0, the oscillator is started. when set to logic 1, the oscillator is stopped when the device switches to v bat . this bit is clear (logic 0) when power is first applied. when the device is powered by v cc , the oscillator is always on regardless of the status of the eosc bit. when the oscil - lator is disabled, all register data is static. bit 6 bbsqw: battery-backed square-wave enable. when set to logic 1 with intcn = 0 and v cc < v pf , this bit enables the 1hz square wave. when bbsqw is logic 0, int /sqw goes high impedance when v cc falls below v pf . this bit is disabled (logic 0) when power is first applied. bit 5 conv: convert temperature. setting this bit to 1 forces the temperature sensor to convert the temperature into digital code and execute the temperature compensate algorithm to update the oscillators accuracy. the device cannot be forced to execute the temperature-compensate algorithm faster than once per second. a user-initiated temperature conversion does not affect the internal update cycle. the conv bit remains at a 1 from the time it is written until the temperature conversion is completed, at which time both conv and bsy go to 0. the conv bit should be used when monitoring the status of a user-initiated conversion. see figure 7 for more details. bits 4:3 na: not applicable. these bits have no affect on the device and can be set to either 0 or 1. bit 2 intcn: interrupt control. this bit controls the int /sqw output signal. when the intcn bit is set to logic 0, a 1hz square wave is output on int /sqw. when the intcn bit is set to logic 1, a match between the timekeep - ing registers and either of the alarm registers activates the int /sqw output (if the alarm is also enabled). the corresponding alarm flag is always set regardless of the state of the intcn bit. the intcn bit is set to a logic 1 when power is first applied. bit 1 a2ie: alarm 2 interrupt enable. when set to logic 1, this bit permits the alarm 2 flag (a2f) bit in the status reg - ister to assert int /sqw (when intcn = 1). when the a2ie bit is set to logic 0 or intcn is set to logic 0, the a2f bit does not initiate an interrupt signal. the a2ie bit is disabled (logic 0) when power is first applied. bit 0 a1ie: alarm 1 interrupt enable. when set to logic 1, this bit permits the alarm 1 flag (a1f) bit in the status reg - ister to assert int /sqw (when intcn = 1). when the a1ie bit is set to logic 0 or intcn is set to logic 0, the a1f bit does not initiate an interrupt signal. the a1ie bit is disabled (logic 0) when power is first applied .
ds3232m 5ppm, i 2 c real-time clock with sram 16 figure 7. conv control bit and bsy status bit operation v cc powered v ba t powered internal 1hz clock bsy conv internal 1hz clock bsy conv the user sets the conv bit the user sets the conv bit 10 seconds the device clears the conv bit after the temperature conversion has completed the device clears the conv bit after the temperature conversion has completed bsy is high during the temperature conversion
ds3232m 5ppm, i 2 c real-time clock with sram 17 status register (0fh) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 osf bb32khz 0 0 en32khz bsy a2f a1f 1 1 0 0 1 x x x bit 7 osf: oscillator stop flag. a logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period and could be used to judge the validity of the timekeeping data. this bit is set to logic 1 any time that the oscillator stops. this bit remains at logic 1 until written to logic 0. the following are examples of conditions that can cause the osf bit to be set: 1) the first time power is applied. 2) the voltages present on both v cc and v bat are insufficient to support the oscillator. 3) the eosc bit is turned off in battery-backed mode. 4) external influences on the oscillator (i.e., noise, leakage, etc.). bit 6 bb32khz: battery-backed 32khz output (bb32khz). this bit enables the 32khz output when the device is pow - ered from v bat (provided the 32khz output is enabled with the en32khz bit). if bb32khz = 0, the 32khz output is forced low when the device is powered by v bat . bits 5:4 unused (0). these bits have no meaning and are fixed at 0 when read. bit 3 en32khz: enabled 32.768khz output. this bit enables and disables the 32khz output. when set to a logic 0, the 32khz output is high impedance. on initial power-up, this bit is set to a logic 1 and the 32khz output is enabled and produces a 32.768khz square wave if the oscillator is enabled. bit 2 bsy: busy. this bit indicates the device is busy executing temperature conversion function. it goes to logic 1 when the conversion signal to the temperature sensor is asserted, and then it is cleared when the device has completed the temperature conversion. see the block diagram for more details. bit 1 a2f: alarm 2 flag. a logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers. if the a2ie bit is logic 1 and the intcn bit is set to logic 1, int /sqw is also asserted. a2f is cleared when written to logic 0. this bit can only be written to logic 0. attempting to write to logic 1 leaves the value unchanged. bit 0 a1f: alarm 1 flag. a logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. if the a1ie bit is logic 1 and the intcn bit is set to logic 1, int /sqw is also asserted. a1f is cleared when written to logic 0. this bit can only be written to logic 0. attempting to write to logic 1 leaves the value unchanged.
ds3232m 5ppm, i 2 c real-time clock with sram 18 aging offset register (10h) temperature registers (11h C 12h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sign data data data data data data data 0 0 0 0 0 0 0 0 the aging offset register takes a user-provided value to add to or subtract from the factory-trimmed value that adjusts the accuracy of the time base. use of the aging offset register is not needed to achieve the accuracy as defined in the electrical characteristics tables. the aging offset code is encoded in twos complement, with bit 7 representing the sign bit. one lsb typically represents a 0.12ppm change in frequency. the change in ppm per lsb is the same over the operating temperature range. positive offsets slow the time base and negative offsets quicken the time base. temperature register (upper byte = 11h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sign data data data data data data data 0 0 0 0 0 0 0 0 temperature register (lower byte = 12h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 data data 0 0 0 0 0 0 0 0 0 0 0 0 0 0 temperature is represented as a 10-bit code with a resolution of 0.25c and is accessible at location 11h and 12h. the tem - perature is encoded in twos complement format. the upper 8 bits, the integer portion, are at location 11h and the lower 2 bits, the fractional portion, are at location 12h. for example, 00011001 01b = +25.25c. upon power reset, the registers are set to a default temperature of 0c and the controller starts a temperature conversion. the temperature is read upon initial applica - tion of v cc or i 2 c access on v bat and once every second afterwards with v cc power or once every 10s with v bat power. the temperature registers are also updated after each user-initiated conversion and are read only.
ds3232m 5ppm, i 2 c real-time clock with sram 19 test register (13h) sram (14hCffh) figure 8. software reset i/o execution bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name: swrst 0 0 0 0 0 0 0 por*: 0 0 0 0 0 0 0 0 * por is defined as the first application of power to the device, either v bat or v cc . this register is used for factory test. bits 6:0 are locked and always read as zeros. writing to bit locations 6:0 has no affect on the device. if the swrst bit is set to logic 1, the device immediately resets all internal logic and registers (except the sram) to their factory-default por state. the device reset occurs during the normal acknowledge time slot following the receipt of the data byte carrying that swrst instruction; a nack occurs due to the resetting action (see figure 8). the i/o master should terminate the i/o string with a nor - mal stop instruction (on the 28th scl clock). the swrst bit is automatically cleared to logic 0. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name: d7 d6 d5 d4 d3 d2 d1 d0 por*: x x x x x x x x * por is defined as the first application of power to the device, either v bat or v cc . sda 11 11 11 0 000 00 00 00 0000 00 0 1 scl slave address register address slave acks nack during swrst data r/w
ds3232m 5ppm, i 2 c real-time clock with sram 20 i 2 c serial port operation i 2 c slave address the devices slave address byte is d0h. the first byte sent to the device includes the device identifier, device address, and the r/ w bit ( figure 9 ). the device address sent by the i 2 c master must match the address assigned to the device. i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses and start and stop conditions. slave devices: slave devices send and receive data at the masters request. bus idle or not busy: time between stop and start conditions when both sda and scl are inac - tive and in their logic-high states. when the bus is idle, it often initiates a low-power mode for slave devices. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. see figure 1 for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high generates a stop condition. see figure 1 for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data transfer to indicate that it immediately initiates a new data transfer following the current one. repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identi - cally to a normal start condition. see figure 1 for applicable timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold time requirements (see figure 1 ). data is shifted into the device during the rising edge of the scl. bit read: at the end of a write operation, the master must release the sda bus line for the proper amount of setup time (see figure 1 ) before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the pre - vious scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master generates all scl clock pulses including when it is reading bits from the slave. acknowledge (ack and nack): an acknowledge (ack) or not acknowledge (nack) is always the ninth bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by trans - mitting a 0 during the ninth bit. a device performs a nack by transmitting a 1 during the ninth bit. timing for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. byte write: a byte write consists of 8 bits of informa - tion transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgment from the slave to the master. the 8 bits transmitted by the master are done according to the bit write definition and the acknowledgment is read using the bit read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to terminate communication so the slave returns control of sda to the master. figure 9. i 2 c slave address byte 11 1 0r /w 0 0 0 msb lsb read/ write bit device identifier
ds3232m 5ppm, i 2 c real-time clock with sram 21 slave address byte: each slave on the i 2 c bus responds to a slave address byte sent immediately following a start condition. the slave address byte contains the slave address in the most significant 7 bits and the r/ w bit in the least significant bit. the devices slave address is d0h and cannot be modi - fied by the user. when the r/ w bit is 0 (such as in d0h), the master is indicating it writes data to the slave. if r/ w = 1 (d1h in this case), the master is indicating it wants to read from the slave. if an incor - rect slave address is written, the device assumes the master is communicating with another i 2 c device and ignore the communication until the next start condi - tion is sent. memory address: during an i 2 c write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte transmitted during a write operation following the slave address byte. i 2 c communication see figure 10 for an i 2 c communication example. writing a single byte to a slave: the master must generate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data, and generate a stop condition. remember the master must read the slaves acknowl - edgment during all byte write operations. writing multiple bytes to a slave: to write multiple bytes to a slave, the master generates a start con - dition, writes the slave address byte (r/ w = 0), writes the starting memory address, writes multiple data bytes, and generates a stop condition. reading a single byte from a slave: unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. to read a single byte from the slave, the master generates a start condition, writes the figure 10. i 2 c transactions sla ve address st ar t st ar t 1 1 0 1 0 0 0 sla ve ack slav e ack slav e ack r/w msb lsb msb lsb msb lsb b7 b6 b5 b4 b3 b2 b1 b0 read/ write register address b7 b6 b5 b4 b3 b2 b1 b0 da ta stop single byte write -write control register to 44h mul tibyte write -write da te register to "02" and month register to "11" single byte read -read control register mul tibyte read -read alarm 2 hours and da te v alues st ar t repea ted st ar t d1h master nack stop 1 1010000 00001110 0eh 1 1010001 1101000 0 0 000111 0 d0h 0eh stop va lue st ar t 11010000 00000100 d0h 04h da ta master nack stop va lue da ta 02h 44h example i 2 c transactions typical i 2 c write transaction 01000100 00000010 d0h a) c) b) d) sla ve ack sla ve ack slav e ack sla ve ack sla ve ack sla ve ack slav e ack repea ted st ar t d1h master ack 1 1010001 va lue da ta slav e ack sla ve ack slav e ack st ar t 11010000 00001100 d0h 0ch sla ve ack sla ve ack stop 11h 0001000 1 slav e ack
ds3232m 5ppm, i 2 c real-time clock with sram 22 slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. however, since requir - ing the master to keep track of the memory address counter is impractical, use the method for manipulat - ing the address counter for reads. manipulating the address counter for reads: a dummy write cycle can be used to force the address counter to a particular value. to do this the mas - ter generates a start condition, writes the slave address byte (r/ w = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (r/ w = 1), reads data with ack or nack as applicable, and generates a stop condition. see figure 6 for a read example using the repeated start condition to specify the starting memory location. reading multiple bytes from a slave: the read operation can be used to read multiple bytes with a single transfer. when reading bytes from the slave, the master simply acks the data byte if it desires to read another byte before terminating the transaction. after the master reads the last byte it must nack to indicate the end of the transfer and then it generates a stop condition. applications information power-supply decoupling to achieve the best results when using the ds3232m, decouple the v cc and/or v bat power supplies with 0.1 f f and/or 1.0 f f capacitors. use a high-quality, ceramic, surface-mount capacitor if possible. surface- mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. if communications during battery operation are not required, the v bat decoupling capacitor can be omitted. using open-drain outputs the int /sqw output is open drain and requires an exter - nal pullup resistor to realize logic-high output level. pullup resistor values between 1k i and 10m i are typical. the rst output is also open drain, but is provided with an internal 50k i pullup resistor (r pu ) to v cc . external pullup resistors should not be added. sda and scl pullup resistors sda is an open-drain output and requires an external pullup resistor to realize a logic-high level. because the device does not use clock cycle stretching, a master using either an open-drain output with a pullup resistor or cmos output driver (push-pull) could be used for scl. battery charge protection the device contains maxims redundant battery-charge protection circuit to prevent any charging of the external battery. ordering information package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. + denotes a lead(pb)-free/rohs-compliant package. /v denotes an automotive qualified part. package type package code outline no. land pattern no. 8 so s8mk+1 21-0041 90-0096 part temp range pin-package ds3232mz+ -40 n c to +85 n c 8 so ds3232mz/v+ -40 n c to +85 n c 8 so
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated products, inc. 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 23 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 3/12 initial release 1 8/12 added an automotive qualified part option to the ordering information table 22 ds3232m 5ppm, i 2 c real-time clock with sram

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